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Intel 10nm technology secret: transistor density than TSMC / Samsung 7Nm

via:快科技     time:2018/6/14 14:44:15     readed:402

Is Intel's technology really bad? Obviously not. Although all called xxnm, but in contrast, Intel is undoubtedly the most rigorous, has been in the pursuit of the highest technical indicators, and because of the rapid increase in the difficulty of semiconductor technology, Intel 10nm has been hard to produce.

At present, the Intel 10nm processor has been shipped in a small batch. The known product has only one low voltage and low power Core i3-8121U, which is first launched by Lenovo IdeaPad 330 notebook.

TechInsight analyzed the processor and obtained some amazing discoveries, which directly confirmed the advanced nature of Intel's new technology.

I3-8121U kernel local Microphotograph

The analysis found thatThe Intel 10nm process uses the third generation of FinFET transistor technology, with a density of 100 million 800 thousand transistors per square millimeter (officially declared) and 2.7 times as much as the current 14nm!

As a contrast,The Samsung 10nm process transistor density is only 55 million 100 thousand millimeters per square millimeter, only about half a point of Intel, and 7Nm is 101 million 230 thousand per square millimeter, barely higher than Intel 10nm.

As for 7Nm of TSMC and GF, the density of transistors is even lower than that of Samsung.

In other words,As far as transistor integration is concerned, Intel 10nm is indeed on the same level with its rival 7Nm, and even better.

In addition,The minimum gate spacing (Gate Pitch) of Intel 10nm is narrowed from 70nm to 54nm, and the minimum metal spacing (Metal Pitch) is reduced from 52nm to 36nm, which is also far superior to the opponent.

In factCompared with other 10nm and future 7Nm, Intel 10nm has the best distance reduction index.

The other highlights of Intel 10nm are also:

-Copper and ruthenium (Ru) were used for the first time in the BEOL back-end process, and the latter was a precious metal.

The self-aligned patterning scheme is used for the first time in the back-end and contact bits.

- 6 to 2 tag high density library for super scaling (Hyperscaling)

- COAG (Contact on active gate) technology

Of course, the advanced technical indicators will eventually be converted into competitive products.

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