New wisdom yuan compilation Edit: Yuan Zi
【新智元导读】Turing Award winners take the lead, Tsinghua Berkeley teamed up to create open source chips, with Shenzhen as the root node, comprehensively enhance the RISC-V ecosystem to the most advanced level, become a non-profit organization with the main mission of technology transfer, and output from Industrial-grade intellectual property results in patent litigation.
At present, the chip market is dominated by Intel, AMD, ARM, Qualcomm and other vendors. A while ago, major chip manufacturers stopped supplying to Huawei, causing Huawei's “spare tires” to be turned positive. Thanks to Ren Zhengfei's vision, Huawei began preparing for a spare tire ten years ago, otherwise Huawei's situation will be more difficult than it is now.
Huawei can do R&D by 500 billion. What about other chip manufacturers, especially small and medium-sized manufacturers? Open source chips may be a good choice.
According to The Information, more than 80 technology companies such as Google, Qualcomm and Samsung began to cooperate in the development of RISC-V open source chip design because of the too expensive ARM license.
To this end, ARM sneaked on a website: riscv-basics.com, which listed several questions about RISC-V, including: cost, ecosystem, fragmentation risk, security issues, design verification. Ultimately, due to public opinion, ARM chose to close the site.
Turing Award winners take the lead, Tsinghua Berkeley teamed up to create open source chips
Clearly, RISC-V has received more and more attention. According to Tsinghua University news, on June 12th, local time, Turing Award winner David · David Patterson announced in Switzerland that he will rely on Tsinghua-Berkeley Shenzhen Institute (TBSI) to build RISC-V international open source experiment RISC-V International Open Source Laboratory, also known as David · Patterson RIOS Turing Award Lab.
David · Patterson is the winner of the 2017 Turing Award, Fellow of the American Academy of Sciences, College of Engineering, School of Arts and Sciences, Pardee Honorary Professor of the School of Electrical Engineering and Computer Science at the University of California at Berkeley, Honorary Doctor of Tsinghua University, Google Distinguished Engineer, RISC- Founder of the V Foundation.
Tsinghua University said that RIOS Lab will aim at the new direction of the world CPU industry strategy development and the industrial innovation needs of Guangdong, Hong Kong and Macau, and focus on the RISC-V open source instruction set CPU research field, and build RISC-V with Shenzhen as the root node. Global innovation network.
It is reported that the RIOS laboratory was established with three missions:
David · Patterson said that he will personally serve as the laboratory director, and his disciple Dr. Tan Zhangqi (TBSI part-time professor) will serve as deputy director. The lab currently consists of 50 full-time engineers who will actively connect with the University of California at Berkeley and the law school at Tsinghua University on issues related to intellectual property law.
Now the lab is actively seeking cooperation between the academic community and the industry. Anyone who has suggestions can send an email to email@example.com.
What is RISC-V?
The readers of Xinzhiyuan do a lot of software and may need to do a little science. To know what RISC-V is, the first thing to know is RISC.
According to Wikipedia,Reduced instruction set computing (English: reduced instruction set computing, abbreviation: RISC) or simply translated as a reduced instruction setIs a design pattern of the computer central processor. Originally from the 1980s by Turing Award winner David · Patterson at the University of California at Berkeley hosted the Berkeley RISC program.
This design idea can be imagined as a pipeline factory, which has simplified the number of instructions and addressing modes, making it easier to implement, more parallel execution of instructions, and higher efficiency of the compiler.
The current common reduced instruction set microprocessors include DEC Alpha, ARC, ARM, AVR, MIPS, PA-RISC, Power Architecture (including PowerPC, PowerXCell), and SPARC.
andRISC-V is an open instruction set architecture (ISA)It started in UC Berkeley in 2010 and was first released in 2011. It is based on the popular Reduced Instruction Set (RISC), which is the same as ARM, MIPS and other common commercial processor architectures. The difference is that it is open source and based on the BSD protocol.
The RISC-V instruction set is freely available for any purpose compared to most instruction sets, allowing anyone to design, manufacture, and sell RISC-V chips and software. Features are modular, simplified, and extensible, allowing you to design an appropriate instruction set based on your scenario.
While this is not the first open source instruction set, it is important because it is designed to work with modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems. Designers have considered performance and power efficiency in these applications. The instruction set also has a number of supported software, which addresses the usual weaknesses of the new instruction set.
Currently RISC-V has grown into a global collaborative project spanning multiple universities and industries. Its consistency is guaranteed by the non-profit RISC-V Foundation (https://riscv.org/), which guides both the underlying instruction set architecture (ISA) specification and the role of the market engine to promote RISC-V.
Last December, the RISC-V Foundation and the Linux Foundation signed a partnership agreement to promote the open source CPU instruction set. The Chinese government has also formed a RISC-V alliance to promote the establishment of the RISC-V ecosystem.
Bao Yungang, secretary general of the RISC-V China Alliance and a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences, believes that the RISC-V instruction set is expected to become the cornerstone of computer chip and system innovation like Linux in the open source software ecosystem, and hopes to use it for about 10 years. By 2030, the establishment of the open source chip ecosystem will be gradually completed.