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Why can TSMC produce the world's first 5nm soon after Intel produces 10nm?

via:博客园     time:2019/6/20 21:54:36     readed:249

In the past few decades, Moore's Law has made processor performance improve rapidly. With the slowdown of Moore's Law, the contradiction between performance and demand has become increasingly obvious. On the one hand, smartphones, HPC and AI are increasingly demanding processor performance, on the other hand, semiconductor process upgrading is becoming more and more difficult and costly. However, advanced semiconductor manufacturing process is still the most intuitive way to improve processor performance, so advanced manufacturing process is more concerned by the industry.

When Intel's 10nm process was delayed again and again, TSMC had already produced 7Nm in volume. When Intel's 10-nm process will be mass-produced in 2019, TSMC will produce 5-nm process in the first half of 2020. Why can the once backward TSMC achieve today's success?

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This week, TSMC held its annual China Technology Forum in Shanghai, but it was the first time that TSMC invited domestic media to participate in its annual technology event. Lei Feng (Public No. Lei Feng) was invited to attend. In his speech at the Technical Forum,According to Wei Zhejia, the global president of TSMC, all 7Nm products currently on the market come from TSMC. He also revealed that TSMC's 5nm technology already has customers designing products based on this technology, and will be mass-produced in the first and second quarter of 2020.

Two Technical Nodes from Backward to Backward

First of all, it needs to be clear that the success of TSMC today is not the result of overnight efforts, and today's advantages do not represent future success. The world's largest wafer manufacturer was founded in 1987, headquartered in Hsinchu, Taiwan, China. When TSMC was founded, semiconductor giants were all IDM models, that is, a company had to complete all the work from design to manufacturing to sealing. That's because it's not easy for wafer-free chips companies to have Wafer Factory giants make chips for them after they have finished designing them.

The founder of TSMC, Zhang Zhongmou, returned to Taiwan from the United States and seized the opportunity to set up TSMC, which specializes in wafer manufacturing, or chip manufacturing. The commercial innovation of TSMC now seems to have a profound impact on the development of the semiconductor industry, but at the beginning of its establishment, the semiconductor industry was in a downturn, and its chip manufacturing technology lagged far behind the chip giants such as Intel, so they had to rely on a small number of orders to survive.

But great entrepreneurs can always lead the company to solve the challenges. Under the leadership of Zhang Zhongmou, with Intel certification endorsement and the warming of semiconductor market, TSMC's revenue ushered in rapid growth. In 1995, revenue exceeded $1.3 billion, and in 1997 it reached $1.3 billion. The huge profit of $535 million made TSMC the most profitable Taiwanese company at that time.

However, it was 20 years after its establishment that TSMC gradually took the lead in technology.In 1999, TSMC led the industry in the production of 0.18 micron copper process manufacturing services.In 2001, TSMC launched the industry's first set of reference design process, helping to develop 0.25 micron and 0.18 micron customers to reduce design difficulties, in order to achieve the goal of rapid mass production.

In 2005, TSMC led the industry in successfully trial-producing 65nm chips. At this time, with the further reduction of transistor volume and the increase of difficulty, the cost rises sharply. Many chip giants have stopped investing in advanced wafer factories, which brings opportunities to Taiji Electric Power Company, which specializes in wafer manufacturing services.

The technical node to further expand the strength of TSMC is 28nm.When entering the 28nm process, there is a key technical choice

In order to consolidate its advantages, TSMC has launched four versions of the mainstream process for Smartphone chip design. The new process not only improves the speed of the previous generation, but also saves 30% of the power by minimizing the size of the chip. As a result, TSMC has built a high barrier at 28 nm nodes.

Three Key Points for the Success of TSMC

Wei Zhejia said that the success of TSMC mainly depends on three supporting points: technology, production and trust from all of you.

为什么英特尔量产

Wei Zhejia, Global President of TSMC

technology roadmap

为什么英特尔量产

According to TSMC, TSMC 7nm has obtained 60 new NTO (New Tape Out, products). After breaking through 100. 7 nm in 2019, TSMC launched the 7nm process. As the first node of TSMC to make EUV lithography technology, the logical density of 7nm is 1.2 times of that of 7nm, and the good rate is as good as that of mass-produced 7nm.According to the plan, TSMC 7nm will be put into mass production in the second half of 2019.

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After 7nm, the first step of TAIC launched was not 6nm but 5nm. Wei said that 5 nm ecosystem design has been completed and that customers can start designing products on the basis of their technology. 5 nm is already in risk pilot production and is expected to begin mass production from Q1 to Q2 2020. After 5 nm, 5 nm is also planned for the power accumulation in Taiwan.

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Wei Zhe explained that 6nm (N6) chose to be launched after 7nm and 5nm because of the experience of 7nm and 5nm to make 6nm have better logical density than 7nm and be compatible with IP of 7nm. IP using 7nm process can continue to use 6nm process to reduce the complexity of the process and reduce the cost.

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According to Lei Feng,In the planning of TSMC, 7Nm will be a transitional node, while 6nm will be a major node, which is expected to play an important role for a considerable period of time.

Capacity investment

Wei Zhejia said that in 2018, Taijiquan's production capacity was 12 million 12-inch wafers, 11 million 8-inch wafers and 8-inch wafers, an average annual increase of 14.3% compared with 2013, an increase of 5.4 million wafers. The continuous growth of production capacity is due to continuous investment. Taiji Nanjing Power Plant (Fab 16), which started construction at the end of last year, is mainly a 16-nm wafer manufacturer. In addition, the 18 plant of TSMC in Tainan started construction in January last year, mainly focusing on the 5-nm process.

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It is reported that,The capital expenditure of TSMC is nearly 10 billion US dollars a year, and the total investment in the past five years is nearly 50 billion US dollars.This year's figure is expected to exceed $10 billion.

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HoweverWei Zhejia emphasized that what really matters is not production, but the quality of production.He said:If the quality of the product is not good enough, don't let it out.

Another key factor in the success of TSMC

How does TSMC keep ahead?

From the current situation, TSMC has achieved the leading position in advanced semiconductor technology, which is a virtuous circle behind it. In wafer OEM, the cost of advanced process is very high at the beginning of mass production. Only a large number of production can reduce costs quickly. Cost and technological advantages can help the OEM obtain higher profits. Finally, the revenue can be used to promote the research and mass production of more advanced process.

Take TSMC for example, their annual capital expenditure is 10 billion or even higher. If they can't make enough profit from advanced manufacturing process, it is difficult to support the research and development of more advanced technology. After all, with the increase of the complexity of semiconductor technology, both R&D and production cost will increase substantially. At the same time, the contribution of advanced process to revenue lags behind. From the revenue of TSMC, we can see that a number of 7Nm processors have been produced last year, but 7Nm contributed little to the revenue at that time. By 2019 Q1, TSMC's 7Nm revenue has reached 22%, which is also the node that contributed the most to the revenue.

Obviously, TSMC has entered a virtuous cycle, and in the wafer manufacturing market, the leader will gain the most profits by virtue of technology and time advantage. Even if the market ranks second, there is a huge gap between revenue and market leader. In this case, it is very difficult to achieve surpassing.

However, even with its advantages, TSMC remains in awe of the market and competitors. Now, TSMC is trying to expand the advantages of logic to more fields. After entering 28nm, the improvement of chip performance through transistor miniaturization has been facing great challenges, and the industry has begun to explore the use of packaging to improve performance. TSMC took the lead in layout and introduced Bumping service. According to TSMC, more than 90% of 7Nm customers now choose TSMC's Bumping service.

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In the third quarter of 2011, Zhang Zhongmou threw a blockbuster without warning --- TSMC is going to enter the packaging field. The first advanced packaging product they launched was CoWoS (Chip on Wafer on Substrate), specifically putting logic chips and DRAMs on silicon interposer and then encapsulating them on a substrate.

Nowadays, the packaging technology of TSMC is mainly divided into two integration technologies: Frontend 3D SoIC and WoW, and Backend 3D Bump/WLCSP, CoWoS and InFO. These technologies help to promote system-level innovation and face different markets.

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It is reported that CoWoS is mainly oriented to AI, servers and networks. InFO_PoP will be mainly applied to mobile phones, InFO_MS to AI reasoning, and InFO_oS to network.In the future, 3D packaging will play a very important role in high performance computing. It is very important for TSMC to have advanced packaging technology. However, TSMC is not ready to compete with the sealer for the market. TSMC says it will focus on wafer-level packaging.

As the main technology to promote the development of semiconductor industry in the future, TSMC is also exploring the possibility of RF and analog devices. In the Wi-FI and millimeter-wave markets, TSMC is pushing the process to 16nm FinFET. In addition, TSMC will launch 7Nm RF, and relevant Spice and SDK will be ready in the second half of 2020. In terms of simulation, TSMC also has a wide layout.

TSMC also has corresponding technologies in mobile image sensor, high-sensitivity MEMS, high-end OLED, PMIC. In the storage area, TSMC's 40nm RRAM will be put into trial production in the first half of 2018, and the 28nm/22nm RRAM will also be put into trial production in the second half of 2019. TSMC also has 22nm MRAM, which is three times faster than eFlash, and the process began to be put into production at risk in the second half of 2018.

Finally, it is important to note that the two keys to semiconductor process improvement are transistor structure and materials. TSMC did not disclose new news about the progress of the structure, but the material aspect mentioned the innovation Low.

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Summary of Leifeng Network

After more than 30 years, TSMC has successfully changed from a backward follower to a leader, and is also the backup of advanced processors. However, TSMC, which is leading in the field of wafer OEM and is in a benign period, still keeps its awe of the market and all its competitors. It is not only improving the continuous investment of transistor structures and materials, which are key to semiconductor manufacturing process, but also trying to maintain its logical advantage. It is also expanding its logical advantage to 5G, simulation and other fields. Moreover, the over 1000 engineers in TSMC Ecology are also an advantage that it is difficult to surpass.

As for storage, TSMC has some layout, but how to gain a leading edge in this field, TSMC's thinking is to focus on new storage technology rather than existing technology, which may be one of the important factors for TSMC's success. Of course, the new technology is also the most likely motive force for the acquisition of TSMC.

Another point is that technology may not be the most difficult to upgrade the future process technology, and the biggest challenge may come from cost considerations.

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