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PCIe 5.0 Show! Is PCIe 4.0 out of date at birth?

via:博客园     time:2019/10/12 8:00:27     readed:974

Author: Q above

PCIe 4.0 products are coming out one after another, but the next generation of PCIe 5.0 has been eager to come. The standard specification has just completed less than half a year. It has been adopted by a number of products and technologies, such asIntel 10nm Agilex FPGAFor exampleCXL,CCIX,Gen-Z High Speed Interconnection Standard

Recently, (Synopsys), a chip development tool and silicon chip IP factory, unveiled its own PCIe 5.0 CXL,PCIe 5.0 CCIX solution, which is also the first time PCIe 5.0 has publicly shown its muscles.

PCIe

CXL and CCIX are interconnection protocols between chips. They are used to connect processors and accelerators (scalar/vector/matrix/space, etc.) and maintain low latency memory and cache consistency. They are all oriented to heterogeneous computing architectures.

Both CXL version 1.0/1.1 and CCIX version 1.1 introduce PCIe 5.0, which takes advantage of its single link 32GT/s high bandwidth and supports different link bandwidth naturally.

PCIe

The DesignWare CXL IP scheme recently introduced by Xinsi Technology can be manufactured in 16nm, 10nm, 7nm process and supports 16 PCIe links, including CXL 1.1 controller, silicon verified PCIe 5.0 controller, silicon verified 32GT/s PHY physical layer, RAS,VC verification IP..

PCIe

DesignWare CCIOX 1.1 IP solution has not yet been officially released, but from the presentation, its functions are complete, and PCIe 5.0 has been well integrated into it.

Both presentation schemes are based on FPGA and special devices without the use of real chips, so it's just a functional demonstration, and it's still some time before the actual product, but it no doubt suggests that PCIe 5.0 will come faster than we thought.

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