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Amd shares information related to Zen 2 architecture on ISSCC 2020: cost control of architecture re analysis

via:Expreview超能网     time:2020/2/28 16:53:02     readed:52

The first is the characteristics of Zen 2 architecture. It is an architecture that can completely cover the current market. It can be competent from server to mobile. A core architecture spans almost all platforms.

Picture from PC watch, same below

Compared with Zen architecture, Zen 2 architecture has a lot of changes, including the use of a new "stage" branch predictor, optimized L1 instruction cache, double microinstruction cache, double floating-point unit data width, third generation AGU, increased various schedulers, instruction storage queues, double L1 data cache read and write bandwidth, and a single CCX has twice L3 cache. The above change resulted in an increase of more than 15% of the IPC of Zen 2 compared with Zen.

Here is a photomicrograph of the single kernel of Zen 2. Amd has marked different functional divisions.

The L3 cache on each CCX can be subdivided into 4 groups, each 4MB in size.

The single CCX of Zen 2 is an old four core 16MB L3 configuration.

But interestingly, amd also introducedTwo new CCX configurationsOne is the four core 4MB L3 configuration used on the ryzen 4000 series APU just released,In addition, there is a dual core 4MB L3 configuration that has not yet seen the actual product

Next, we will talk about the differences between Zen and Zen 2. One is the 14 nm FinFET process of GF, and the other is the 7 nm FinFET process of TSMC.

It can be seen that the new process has brought a considerable increase in transistor density. Under the same four core configuration, the area of Zen 2 single CCX is 12.7mm smaller than Zen's single CCX under the condition of L3 multiplicationTwo.

The progress of the process is the main source of the significant improvement of the energy efficiency ratio of Zen 2, but it can also be seen that the adjustment of the architecture is also an important factor.

The final goal is to put twice the number of cores in a single slot, that is to say, the largest 64 cores in a single chip are jointly improved by both architecture and technology.

In terms of single core performance, Zen 2's single core also saves more power.

In the end, Zen 2 made great progress.

This slide shows different packaging strategies adopted by processors in different markets. It can be seen that CCD is the same, while IO die is very different: desktop level IO die is used on ryzen series desktop processors, with an area of 125mmTwoOn epyc 2 and ryzen threadriver, server level IO die is used, with an area of 416mmTwo

In the future, we will continue the 7 nm process of QCM, which helps to reduce the area of a single CCD. Here, amd also gives the reason why they adopt MCM. Because many tasks are IO intensive on the server and desktop side, for this part of the unit, better technology will not bring significant performance improvement, but will increase many costs. So amd chooses to partition the whole processor (in fact, SOC), decouple the CPU core from Io and memory, and the later modules are manufactured by the old generation technology.

In addition, why is the Zen 2 processor actually a SoC? Because there are some other microprocessors integrated on it, either for power management or for temperature monitoring.

Amd then introduces some details of the MCM package, including the circuit layout of inter chip interconnection and the layout of the base pin circuit.

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In the end, the chiplet multichip solution helps them save a lot of costs on the server products. The official figure is that 48 core products save about 100% of the cost, while 16 core products save about 40% of the cost.

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Similarly, on the desktop, chiplet also has a considerable cost advantage. The common eight core products can save about 20-30%, while the 16 core products can save 100% of the cost. Even this IO die can be used to make x570 chipset.

In any case, Zen 2 is a very successful generation processor architecture. In terms of microcosmic aspect, the core IPC is 15% higher than that of the previous generation, which is close to the level of the architecture that rivals have used for many years. With the help of TSMC 7Nm technology, it has also achieved significant progress in energy consumption ratio. On the macro level, the use of chip multi chip packaging mode enables AMD to effectively control the cost of the product. In addition, the advantage of the product line is that it has considerable scalability. Add a core to the substrate, and if you can't, replace the large substrate, and replace the large IO die. Finally, we see that AMD is rapidly spreading Zen 2 product line, from six cores to 64 cores, provides customers with a wide range of choices, and new mobile oriented processors are ready to be launched, we will see it soon.

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