Apple A14, Samsung exynos 1080, Kirin 9000, snapdragon 888 and other chips all use 5nm technology. In this regard, TSMC and Samsung account for half. According to the current roadmap, 5nm technology will be upgraded slightly next year. So 3nm technology, as an iterative identity, will have to wait until 2022.
Following the announcement of TSMC's large-scale production plan of 3nm in 2022, foreign media reported that TSMC plans to start the production of 3nm plus enhanced version in 2023. There is no doubt that Apple will still be the first.
If there is no accident, 3nm plus will be launched on the A17 processor on the iPhone 15
If Apple's naming rules remain unchanged, the corresponding A17 processor should be used on the iPhone 15 in 2023. Of course, the M-series processors on the Mac will certainly be used. By then, Apple may no longer have Macs with Intel processors.
According to previous reports, 3nm will achieve 15% performance improvement, 30% power reduction and 70% transistor density increase. The specific parameters of 3plus are not clear.
Although TSMC does not disclose the changes of 3nm plus compared with 3nm, it will obviously have higher transistor density, lower power consumption and higher operating frequency.
In terms of technology, TSMC's 3nm still uses FinFET fin FET, while Samsung's 3nm uses the more advanced GAA surround gate transistor method.
In this regard, TSMC believes that the current FinFET process has better cost and energy efficiency. Therefore, the first 3 nm chips will still use FinFET transistor technology. However, Samsung, TSMC's old rival, is betting on the launch of 3nm nodes. Its progress and technology selection are very radical. It will abandon FinFET transistors and use GAA to surround gate transistors directly.
As early as April this year, TSMC announced some details of 3nm technology. Its transistor density set a new record of 250 million / mm2. For comparison, Kirin 9905g and TSMC have a 7 nm EUV process with a size of 113.31mm2, a transistor density of 10.3 billion, and an average of 90 million / mm2. However, the transistor density of the 3 nm process is 3.6 times higher than that of the 7 nm process. This density is visually similar to reducing the Pentium 4 processor to the size of a needle.
3nm process: mass production in 2022, apple a16 chip will be launched
TSMC has prepared a total of four waves of capacity for the 3nm process. Most of the first wave of production capacity will be reserved for apple, its big customer for many years. The latter three waves of capacity will be reserved by manufacturers such as Qualcomm NVIDIA.
The fabrication method of N3 is FinFET transistor structure, which is suitable for mobile and high performance computing applications.
TSMC has said that 3nm follows fineft technology, mainly considering that customers can use the 5nm process design in the 3nm process, without the need to redesign the product. TSMC can maintain its cost competitiveness and obtain more customer orders. It is reported that the new node uses EUVL technology for up to 20 layers of lithography, which is currently no new technology can do.
In the more distant 2 nm process, TSMC will abandon its FinFET (fin type field effect transistor) for many years, or even use the gaafet (surround gate field effect transistor), or nanowire, which Samsung plans to use in the 3 nm process. Instead, it will expand it to mbcfet (multi bridge channel field effect transistor), or nanosheets.
FinFET's capability has reached the bottom, and the cooling problem of new technology has not been solved
Transistor is one of the key building blocks in the chip, which can provide switching function in the device. The market predicts that the fate of 5nm may follow the footsteps of 10nm and become a transition from 6nm to 3nm.
As chips move to 3 nm and more advanced processes, FinFET capabilities have bottomed out, and some generation plants hope to move to the next generation transistor called nanosheet FET by 2022. Nanosheet FET belongs to the so-called gate all around FET.
Nanosheet FET is an extension of FinFET. It's flanked by a FinFET, which is surrounded by a grid. The nanosheets will appear at 3 nm and may extend to 2 nm or even 1 nm.
There are also other gate all around categories, for example, IMEC is developing 2 nm forksheet FET, complex FET (CFET).
In the forksheet FET, nFET and pFET are integrated in the same structure, with 42nm contact gate spacing (CPP) and 16nm metal spacing, allowing tighter n-to-p spacing and reducing area scaling.
Photolithography is a technique of composing fine graphics on a chip, which is helpful to realize chip scaling. However, in the 5nm process, the current optical based 193nm lithography scanner has done its best.
In the process of 3 nm and above, chip manufacturers may need a new EUV lithography technology called high NA EUV. Chipmakers hope that this complex and expensive technology will be developed in 2023.
Throughout the world, there are only three players left: Intel, Samsung and TSMC. Among them, Samsung and TSMC are the only ones that are really focusing on 3nm. Let's wait and see what happens three years later.