With the increasing limitation of semiconductor technology and chip scale, the traditional single large chip strategy is no longer feasible. Chiplet small chip has become a new direction. AMD is undoubtedly the leader among them. Three product lines, including sharp dragon, thread tearing and Xiaolong, are practicing this principle and have achieved good results.
Now, AMD is going to extend this strategy to GPU graphics card.
On the last day of 2020, amd submitted a new patent to the U.S. patent and Trademark Office, outlining the future GPU chip design.
Chiplet chip, amd has been playing very well
Amd first pointed out that the traditional multi GPU design has many problems (including AMD's own crossfire). For example, the GPU Programming model is not suitable for multi-channel GPUs, it is difficult to distribute the load among multiple GPUs in parallel, and the synchronization of cache content between multiple GPUs is extremely complex, etc.
In this way, the whole GPU array is regarded as a single SOC, and then divided into sub chips with different functions.
In traditional GPU design, each GPU has its own end cache, but in order to avoid the synchronization problem,Amd also redesigned the cache system. Each GPU still has its own end level cache, but these caches are coupled with physical resources, so all caches are still unified and consistent among all GPUs.
Sounds hard to understand, right? This is true. After all, in patent documents, manufacturers tend to deliberately hide specific design details, and there may even be some descriptions that deliberately make them difficult to understand or even misleading.
Amd did not disclose whether it was actually designing a small GPU chip, butIt has been rumored that the next generation of RNA3 architecture will introduce multi chip. This patent is providing further evidence.
It can be expected that if the rdna3 architecture is really designed on a small chip, the core scale will inevitably expand dramatically, and 10000 or 20000 stream processors are small.
AMD is not the only one with this idea. Intel Xe HP and Xe HPC high performance architecture will adopt tile block based design, which will come out later this year and go straight to high performance computing and data center.
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