AMD is going to change the interface in an all -round way. At the beginning of the Zen4 architecture, the Ryzen 7000 series on the desktop changed from the AM4 interface to AM5, and the Xiaolong 7004 series on the data center changed from the SP3 interface to SP5 and SP6.
The difference is that the SP5 series is a high -performance version with complete specifications. The SP6 series is separated by edge computing and telecommunications infrastructure applications. It only supports single -road configuration, and the specifications are also streamlined a lot.
Today, some overseas netizens leaked further details of the SP6 interface, including physical maps and design drawings.
AMD Xiaolong continues the three generations of SP3 interfaces, also known as LGA4094, which is 4094 contacts.75.4 & Times; 58.5 mm.
The SP5 interface, also known as LGA6096, naturally 6096 contacts, which increased almost half, and the length and width size increased to the size80.0 & Times; 76.0 mmThe area increased by nearly 38 %.
The alias of the SP6 interface are LGA4844, with a total of 4844 contacts, which is more than 20 % less than the SP5, but it is still about 18 % more than SP3, while the length and width size remain at 75.4 & times; 58.5 mm.
Of course, SP3, SP5, and SP6 are not compatible with each other.
There are guessing that Zen4 Genoa and Zen4C Bergamo of the SP5 interface will be named Xiaolong 7004 series, and Z of the SP6 interface will be named Xiaolong 5004 series to distinguish.
Discover showing,The GENOA series of the SP5 interface has a maximum of 96 Zen4 cores and 192 threads. The power consumption range is 200-400W. The BERGAMO series has up to 128 Zen4C cores and 256 threads, with a power consumption range of 320-400W.
They all support one -way and dual -road configuration, 12 -channel DDR5 memory, 160 PCIE 5.0 bus, 12 PCIE 3.0 bus, 64 CXL V1.1+high -speed interconnected bus.
Genoa also has a derivative version & ldquo; Genoa-X & RDQUO;, similar to the current Milan-X, also adds 3D V-Cache stack cache.
The SP6 interface version is up to 32 Zen4 cores or 64 Zen4C cores, and the power consumption range is reduced to 70-225W.
At the same time, it is streamlined to 6 -channel DDR5, 96 PCIE 5.0, 8 PCIE 3.0, 48 CXL 1.1+, which is the specifications of one -third to half.
The product code of Zen5 architecture & ldquo; Turin & rdquo; (Turin) also has two interface versions: SP5 and SP6, but the specific specifications are not clear for the time being. It is expected that there will be up to 256 core 512 threads and 12-channel DDR5-6000.