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TSMC announces 2nm process for the first time, mass production in 2025 | silicon-based world

via:凤凰网     time:2022/6/17 12:01:45     readed:51

2021年6月9日,有观众在南京的世界半导体大会台积电展台拍摄(图片来源:钛媒体App编辑)

TSMC's booth at the world Semiconductor Congress 2021

The long-rumored 2nm has finally arrived.

On June 17,Taiwan Semiconductor Manufacturing Company (TSMC) officially announced the future advanced process road map at the TSMC North America Technology Forum held early this morning, Titanium Media App learned.

Among them, TSMC's 3nm (N3) process will be mass-produced in 2022, while TSMC's first 2nm (N2) process using nanocrystal transistor (GAAFET) architecture will be mass-produced in 2025.

"In a rapidly changing and growing digital world, the demand for computing power and energy efficiency is increasing faster than ever, opening up unprecedented opportunities and challenges for the semiconductor industry," TSMC President Victor Wei said in an online forum. At a time of exciting transformation and growth, the innovations revealed at the technology Forum demonstrate TSMC's technological leadership and commitment to supporting customers.

Meanwhile, YJ Mii, TSMC's senior vice president of RESEARCH and development, announced at the conference that TSMC will have ASML's latest high-NA Ultra-ULTRAVIOLET (EUV) lithography microlithography equipment by 2024. "Primarily for partner research purposes...... Drive innovation by developing infrastructure and format solutions for customer needs."

台积电制造工艺路线图,2nm于2025年开始量产

TSMC manufacturing process Roadmap, 2nm to start mass production in 2025

Specifically, the core of the TSMC Technology Summit was the unveiling of technical details of the N3 (3nm class) and N2 (2nm class) series of leading nodes, as well as TSMC-3DFabricTM 3D silicon stack solutions, to be used in the manufacture of advanced CPU, GPU and mobile SoC chip products in the coming years.

3nm technology node:TSMC's first 3nm class node, called N3, is expected to start mass manufacturing (HVM) in the second half of this year, with deliveries to customers expected in early 2023. The 3nm second node N3E, compared to the N5, has a 34% reduction in power consumption, 18% improvement in performance and 1.6 times increase in logic transistor density at the same speed and complexity. Coupled with the advanced TSMC FinFlextm architecture, the N3E can precisely assist customers to complete the single-chip system design to meet their needs.

2nm node: TSMC's first 2nm node, called N2, is based on nanosheet transistor (GAAFET) architecture and is expected to start mass production in 2025.It is reported that under the same power consumption, 2nm performance speed is 10% to 15% faster than 3nm, if at the same speed, power consumption is reduced by 25% to 30%. TSMC also said that the 2nm process technology platform also covers efficient versions and complete Chiplet integration solutions.

Extended ultra-low power platform:TSMC said it is developing N6e technology to focus on edge artificial intelligence and Internet of Things devices. The N6e will be based on a 7nm process and is expected to have three times more logical density than the previous generation N12e. The N6e platform covers logic, RF, analog, embedded non-volatile memory, and power management IC solutions.

Tsmc-3dfabrictm 3D Silicon Stack solution:TSMC today unveiled two groundbreaking innovations: a SOIC-based CPU that stacks three-stage cache static random access memory using chip-on-Wafer (CoW) technology; The other is an innovative AI SoC that uses wafer-on-wafer (WoW) technology stacked on top of deep groove capacitor chips.

TSMC said that 7nm chips with CoW and WoW technologies are already in mass production, and 5nm technology is expected to be completed in 2023. To meet customer demand for system integration chips and other 3DFabric system integration services, the first fully automated 3DFabric fab is expected to start production in the second half of 2022.

As TSMC 2NM shifts to nanosheet-based GAAFET architecture, the 3NM series will be the last technology platform for TSMC FinFET nodes. TSMC is expected to continue producing 3nm semiconductors after mass production of 2nm chips in 2025.

In addition, TSMC revealed that its capacity at mature and specialist nodes will expand by about 50 percent by 2025. The plan includes the construction of a large number of new fabs in Tainan, Kaohsiung, Japan and Nanjing, a move that will further intensify competition between TSMC and foundries such as GMC, UmC and SMIC.

According to AnandTech, the expansion of mature and professional node investments in four new facilities are:TSMC's Fab 23 Phase I plant in Kumamoto, Japan, will manufacture 12nm, 16nm, 22nm and 28nm chips and will have a production capacity of up to 45,000 300mm (12-inch) wafers per month; Tainan Fab 14, Phase 8; Kaohsiung Fab 22 Phase II; Fab 16 phase 1B in Nanjing mainly produces 28nm mature process chips.

TSMC currently operates 13 foundries around the world. Of these, 10 are in Taiwan, and two are in Shanghai and Nanjing, making 8-inch and 12-inch wafers, respectively. One Fab11 in the United States makes 8-inch wafers. TSMC's 7nm and 5nm advanced process chips are mainly produced at Fab18 plant in tainan.

(Author | Lin Zhijia)

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