IT home December 16, in today's "Second China Interconnection Technology and Industry Conference", the first by the Chinese integrated circuit field related enterprises and experts jointly led the development of the "small chip interface bus technical requirements" group standard formally through the Ministry of Industry and Information Technology China Electronics Industry Standardization Technology Association validation and release.

According to the introduction, this is the first native Chiplet technology standard in China.

In May 2021, the China Computer Interconnection Technology Alliance (CCITA) established the Chiplet standard in the Ministry of Industry and Information Technology (MIIT), i.e., "Small Chip Interface Bus Technical Requirements", which was developed by the Institute of Computing of the Chinese Academy of Sciences, the Fourth Institute of Electronics of MIIT and several domestic chip manufacturers in cooperation.

IT House has reported that on March 28 this year, by the China Computer Interconnection Technology Alliance (CCITA) joint electronic standards institute, a number of enterprises, research institutes, etc. after 10 months of efforts to jointly develop the "small chip interface bus technical requirements", "microelectronic chip optical interconnection interface technology" to complete the draft standard development, began to seek comments for the community.

The "Small Chip Interface Bus Technical Requirements" describes the small chip interface bus (chip-let) technical requirements for CPU, GPU, AI chip, network processor and network switching chip application scenarios, including general overview, interface requirements, link layer, adaptation layer, physical layer and packaging requirements.

According to the introduction, the small chip interface technology has the following application scenarios.

• C2M (Computing to Memory), the interconnection of computing chips to storage chips.

• C2C (Computing to Computing), the interconnection between computing chips. The two are connected in the following way.

• Parallel single-ended signals are used for interconnecting multiple computing chips within the CPU.

• Serial differential signal connection, mostly used for AI, Switch chip performance expansion scenarios.

• C2IO (Computing to IO), the interconnection of computing chips to IO chips.

• C2O (Computing to Others), the interconnection of computing chips with other small chips such as signal processing and baseband units.

This standard lists three interfaces, such as parallel bus, and puts forward a variety of rate requirements, the total connection bandwidth can reach 1.6Tbps, in order to flexibly respond to different application scenarios and technology providers of different capabilities, through the detailed definition of the link layer, adaptation layer, physical layer, to achieve interconnection and interoperability between small chips, and take into account the support of existing protocols such as PCIe, lists the requirements of the packaging method, small chips The design can not only use the international advanced packaging method, but also make full use of the domestic packaging technology accumulation.