With the slow progress of advanced process technology, multi-chip integrated packaging has become a major trend in the semiconductor industry.

At the ISSCC 2023 International Conference on solid-State Circuits, AMD put forward a variety of new ideas for integrated packaging, one of which is to stack DRAM memory directly and multi-layer within the CPU processor.

One way is the CPU computing module, the DRAM memory module, which is encapsulated side by side on the silicon intermediary layer, while the other is to stack the memory module directly above the computing module, which is a bit like the mobile phone SoC.

AMD said that this design allows the computing core to access memory with shorter distances, higher bandwidth and lower latency, and can greatly reduce power consumption. 2.5D packaging can achieve about 30% of the power consumption of independent memory, while 3D hybrid bonding packaging has only the traditional 1R6.

If the stack memory capacity is large enough, the DIMM slot on the motherboard can even be saved.

Of course, AMD's vision is only for servers and data centers, and it won't be done on the desktop, otherwise it can't be upgraded.

AMD even considers that the Instinct series accelerator cards have integrated and encapsulated HBM high-bandwidth memory, and continue to stack DRAM memory on top of the latter, but only one layer, the capacity will not be too large.

The biggest advantage of this is that some key algorithm kernels can be executed directly in integrated memory without having to reciprocate communication between CPU and independent memory, thus improving performance and reducing power consumption.

The biggest advantage of this is that some key algorithm kernels can be executed directly in integrated memory without having to reciprocate communication between CPU and independent memory, thus improving performance and reducing power consumption.

In particular, the introduction of optical network channels can greatly simplify the network infrastructure.

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