In 2021, Intel announced a new manufacturing process roadmap, including Intel 7, 4, 3, 20A, 18A, among which 20A and 18A will lead into the era of Emme, and the RibbonFET fully wrapped grid technology was adopted at the same time.

Fast Technology news on June 6th,Intel announced that it first implemented backside power on a product-level test chip code-named "Blue Sky Creek," which will be rolled out to Intel 20A nodes in the first half of 2024.

In the traditional positive power supply technology, both signal routing and power routing are located on the front side of the wafer, so the resources of each metal layer need to be shared or even competed for. Therefore, the pin spacing of the metal layer must be expanded to increase the cost and complexity.

Backside power supply technology separates signal routing and power routing, and the latter is transferred to the back side of the wafer, which can be separately optimized, bringing higher performance and lower cost, but also facing yield and reliability. Heat dissipation, debugging and other challenges.

In order to accelerate research and development, Intel chose PowerVia and RibbonFET to separate research and development, and PowerVia was taken the lead.

Intel confirmed through testing,The PowerVia technology does offer significant efficiency improvements, with standard cell utilization exceeding 90% in most areas, and significant cost reductions due to a significant reduction in transistor size and cell density.

At the same time, PowerVia has achieved very high yield and reliability indicators in testing, demonstrating the expected value of this technology.

The tests also showed thatPowerVia reduced platform voltage by 30% and resulted in a 6% frequency gain.

In response to this new transistorized power supply, Intel has developed a new heat dissipation technology that demonstrates good heat dissipation characteristics and can avoid overheating.

At the same time, the debugging team also developed new techniques to ensure that the debugging of the new transistor design structure can be properly resolved.

According to previous disclosures, the Intel PowerVia technology test chip uses the Intel 4 manufacturing process, 22 metal layers, a single core area of just 2.9 square millimeters, and a voltage of 1.1V down to 3GHz frequencies.